With the increasing down-scaling of integrated circuits and the increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin Field-Effect Transistors (FinFETs) were thus developed. The FinFETs include vertical semiconductor fins. The semiconductor fins are used to form source and drain regions, and to form channel regions between the source and drain regions. Shallow Trench Isolation (STI) regions are formed to define the semiconductor fins. The FinFETs also include gate stacks, which are formed on the sidewalls and the top surfaces of the semiconductor fins.
In the replacement of dummy gates used in a gate-last fabrication, hard mask layer(s) of nitrides and/or oxides may be formed over a dummy gate electrode, such as polysilicon. Replacing the dummy gate can involve etching the hard masks, however, due to gate loading effects gate heights may have different heights and widths. Etching the hard masks may cause shortening of some of the gates, due in part to gate loading and etch rate variations in the etching chamber.
In a plasma etching process, a gas is first introduced into a reaction chamber and then plasma is generated from the gas. This is accomplished by dissociation of the gas into ions, free radicals and electrons by using an RF (radio frequency) generator, which includes one or more electrodes. The electrons are accelerated in an electric field generated by the electrodes, and the energized electrons strike gas molecules to form additional ions, free radicals and electrons, which strike additional gas molecules, and the plasma eventually becomes self-sustaining. The ions, free radicals and electrons in the plasma react chemically with the layer material on the semiconductor wafer to form residual products which leave the wafer surface and, thus, etch the material from the wafer.